A nonvolatile memory is known as one of the integrated semiconductor memories incorporated in an LSI. This is the element in which stored information is not lost even when the power of the LSI is turned off and is an extremely important element for using the LSI in the various applications. Information can be stored in the nonvolatile memory by various methods. As the nonvolatile memories in which information is stored by means of the amount of trapped charges of electrons and holes, for example, the so-called floating-gate memory in which charges are trapped in a conductive material and the so-called MONOS memory in which charges are trapped in an insulating material are known. Since the MONOS memory cell has the well-known transistor structure except for that of the gate insulating film, it has been known that the MONOS memory cell can be formed in a manner consistent with the CMOS LSI process.
Further, as the applications of the memory cell with the MONOS structure, the application to the large-capacity data storage having the structure in which a floating gate of a NAND flash memory cell is replaced with the MONOS structure is known (Japanese Patent Application Laid-Open Publication No. 2002-280467 (Patent Document 1)). In addition, the application to the embedded microcomputer capable of high-speed writing or erasing and having the structure in which a selection gate is disposed adjacent to a memory gate having the MONOS structure is also known (Japanese Patent Application Laid-Open Publication No. 2006-49737 (Patent Document 2)). Since each memory cell is constituted of one transistor in the former structure, it is possible to reduce the memory cell area. Further, since high-energy charges such as electrons and holes can be used owing to the selection gate disposed adjacent to the memory gate in the latter structure, the high-speed operations in writing or erasing can be achieved. The present invention particularly relates to a technology for achieving the high reliability and the high-speed operation of a memory cell to be applied to the embedded microcomputer described above.
As the writing/erasing operation of a memory cell applied to an embedded microcomputer, the operation in which the charges with different signs are injected instead of injecting and emitting the charges with the same sign, thereby rewriting the stored information has been known (Patent Document 2).
An equivalent circuit of the memory cell described in the Patent Document 2 is shown in FIG. 1, and a cross-sectional structure of the device is shown in FIG. 2 and FIG. 3. FIG. 2 is a cross-sectional view of the memory cell in a source-drain direction and FIG. 3 is a cross-sectional view taken along the line A-A′ in FIG. 2, which shows a cross section in an extending direction of a memory gate. First, the description will be made with reference to FIG. 2. In FIG. 2, a part of the gate insulating film of a memory gate (00002) is a charge trapping layer (00004) and is made of, for example, a silicon nitride film. As an upper layer and a lower layer of the charge trapping layer, insulating films are disposed, and silicon oxide films are used for the insulating films. As described above, the so-called MONOS structure in which a silicon nitride film is sandwiched between silicon oxide films is formed. Next, the description will be made with reference to FIG. 3. In the cross-sectional view of FIG. 3, element isolation insulating films (00006) are formed in a semiconductor substrate (00005), by which the interference of current between adjacent memory cells is prevented and elements are isolated from each other. Further, the region where an element isolation insulating film is present serves as an element isolation region. In other words, the region between the element isolation insulating films serves as an element formation region. More specifically, the region where the element isolation insulating film is not present serves as the element formation region. Also, as is apparent from FIG. 2 and FIG. 3, the conventional memory cell has the structure in which a silicon nitride film to be a charge trapping layer is present also on the element isolation insulating film in the element isolation region.
Next, the operation of the memory cell will be described. As the basic operations of the memory cell, four states such as (1) writing; (2) erasing; (3) holding; and (4) reading are known. Note that the names for these four states are used by way of example, and writing and erasing may be called in an opposite way. Further, the operations will be described based on representative examples, but various different operations have been proposed. Although a memory cell formed of an n MOS will be described here as an example, the memory cell can be formed of a p MOS in the same manner in principle.
(1) The writing operation will be described below. In the writing operation, positive potential is applied to the diffusion layer on the memory gate side (00003), and ground potential equal to that of the semiconductor substrate is applied to the diffusion layer on the selection gate electrode side (00003). By applying the high gate overdrive voltage to the memory gate, the channel below the memory gate is put into an ON state. Then, the potential of the selection gate (00001) is set to the value higher than the threshold value by 0.1 to 0.2 V, thereby putting it into an ON state. At this time, since the strongest field occurs in the vicinity of the boundary of the two gates, many hot electrons are generated and injected into the memory gate side. This phenomenon is known as the source side injection (SSI). The hot electron injection by this writing method is characterized in that, since the field is concentrated around the boundary between the selection gate and the memory gate, the injection is concentrated on the end portion of the memory gate on the side of the selection gate. Further, different from the floating-gate type in which the charge trapping layer is formed of a conductive film, the charge trapping layer is formed of an insulating film, and therefore, the injected electrons are not freely moved in the insulating film and the electrons are held in an extremely narrow region.
The erasing operation will be described below. In the erasing operation, negative potential is applied to the memory gate, and positive potential is applied to the diffusion layer on the memory gate side, thereby generating the strong inversion in the region where the memory gate at the end portion of the diffusion layer and the diffusion layer are overlapped. By doing so, the band to band tunneling (BTBT) occurs, and the holes are generated. In this memory cell, the generated holes are accelerated in the channel direction, drawn by the bias of the memory gate, and injected into the ONO film. In this manner, the erasing operation is carried out. More specifically, the threshold value of the memory gate which has been increased by the charges of the electrons can be reduced by the charges of the injected holes.
(3) The holding operation will be described below. In the charge holding operation, charges are held as the charges of carriers injected into the ONO film serving as an insulating film. Since the movement of the carriers in the insulating film is extremely limited and slow, it is possible to appropriately hold the charges even if no voltage is applied to the electrode.
(4) The reading operation will be described below. In the reading operation, positive potential is applied to the diffusion layer on the selection gate side, and positive potential is applied to the selection gate. By doing so, the channel below the selection gate is put into an ON state. Then, an appropriate memory gate potential capable of distinguishing the difference in threshold values of the memory gate given by the writing state and the erasing state (that is, the intermediate potential between the threshold value in the writing state and the threshold value in the erasing state) is applied. By this means, the conduction and non-conduction of the current can be distinguished, and the held charge information can be read by the current amount.